Semiconductor geometries have been shrinking with each new technology node enabling more and more transistors to be built in the same area. The wavelength of light used to print the ever smaller geometries and spaces between geometries has remained at 193 nm for several generations because of difficulty in making manufacturable photoresists for 157 nm photolithography.
Typically design rules shrink by 30% in going from one technology node to the next to give approximately a 50% reduction in integrated circuit area. (0.7 length×0.7 width=0.49 area). Because of the limitation imposed by the wavelength of light upon the minimum size of geometries that may be printed, some design rules are not able to be reduced as desired. For example, geometries smaller than about 60 nm cannot be printed using 193 nm light, even with enhanced resists. This results in larger chip area and increased cost.
To form geometries smaller than the 193 nm photolithography capability, several geometry reduction techniques have been developed. For example, to form holes that are smaller than 60 nm, one technique is to print the holes at 60 nm and then to heat and reflow the resist causing the hole diameter to decrease by approximately 10 nm. While this technique works for small contact holes, the shape and resist profile of larger contact holes such as rectangular contacts found in SRAMs is unacceptably degraded.
Another technique is to deposit a polymer on the contact sidewalls during contact etch. This may form contacts with sloped sidewalls and a top dimension that is significantly larger than the bottom dimension.
Other techniques termed RELACS™ and SAFIER™ use the reaction between a spin-on polymer and the resist pattern to form a layer of additional polymer on the sides of the photoresist pattern. As with other conventional processes, large geometries such as rectangular contacts shrink more along the longitudinal dimension.
A conventional hole size reduction process is illustrated in FIG. 1. A minimum sized hole 1002 and a rectangular hole 1010 are formed in a dielectric layer 1000. The square 1002 and the rectangle 1010 represent the hole geometries as they appear on the reticle. The broken dashed lines 1004 and 1012 represent the holes as they appear post etch without a hole size reduction process. The solid lines 1006 and 1014 represent the holes as they appear post etch with a conventional hole size reduction process. As can be seen, with a conventional process the longitudinal hole size reduction 1016 is significantly larger than the lateral hole size reduction 1018. This requires the longitudinal hole size to be increased on the reticle to compensate for the additional shrinkage. This may cause the longitudinal hole size to be increased beyond lithographic printing capability in which case adjacent holes may merge when printing. To prevent this may require an increase in longitudinal pitch resulting in increased area and increased cost.